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128-macrocell max? epld cy7c346b cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 document #: 38-03037 rev. ** revised december 8, 1999 46b features ? 128 macrocells in 8 labs 20 dedicated inputs, up to 64 bidirectional i/o pins programmable interconnect array advanced 0.65-micron cmos technology to increase performance available in 84-pin clcc, plcc, and 100-pin pga, pqfp functional description the cy7c346b is an erasable programmable logic device (epld) in which cmos eprom cells are used to configure logic functions within the device. the max architecture is 100% user-configurable, allowing the device to accommodate a variety of independent logic functions. the 128 macrocells in the cy7c346b are divided into 8 logic array blocks (labs), 16 per lab. there are 256 expander product terms, 32 per lab, to be used and shared by the mac- rocells within each lab. each lab is interconnected through the programmable inter- connect array, allowing all signals to be routed throughout the chip. the speed and density of the cy7c346b allow it to be used in a wide range of applications, from replacement of large amounts of 7400-series ttl logic, to complex controllers and multifunction chips. with greater than 25 times the functional- ity of 20-pin plds, the cy7c346b allows the replacement of over 50 ttl devices. by replacing large amounts of logic, the cy7c346b reduces board space, part count, and increases system reliability. macrocell 49 macrocell 50 macrocell 51 macrocell 52 macrocell 53 macrocell 54 macrocell 55 macrocell 56 macrocell 33 macrocell 34 macrocell 35 macrocell 36 macrocell 37 macrocell 38 macrocell 39 macrocell 40 macrocell 104 macrocell 103 macrocell 102 macrocell 101 macrocell 100 macrocell 99 macrocell 98 macrocell 97 macrocell 120 macrocell 119 macrocell 118 macrocell 117 macrocell 116 macrocell 115 macrocell 114 macrocell 113 macrocell 1 macrocell 2 macrocell 3 macrocell 4 macrocell 5 macrocell 6 macrocell 7 macrocell 8 macrocell 17 macrocell 18 macrocell 19 macrocell 20 macrocell 21 macrocell 22 macrocell 23 macrocell 24 logic block diagram c346b ? 1 macrocell 88 macrocell 87 macrocell 86 macrocell 85 macrocell 84 macrocell 83 macrocell 82 macrocell 81 macrocell 121 ? 128 macrocell 105 ? 112 macrocell 86 ? 96 macrocell 41 ? 48 macrocell 25 ? 32 macrocell 9 ? 16 system clock p i a input [59] (n4) 36 . input [60] (m5) 37 . input [61] (n5) 38 . input [64] (n6) 41 . input [65] (m7) 42 . input [66] (l7) 43 . input [67] (n7) 44 . input [70] (l8) 47 . input [71] (n9) 48 . input [72] (m9) 49 . [100] (c13) nc [99] (d12) nc [98] (d13) 77 [97] (e12) 76 [96] (e13) 75 [95] (f11) 74 [92] (g13) 73 [91] (g11) 72 [90] (g12) nc [89] (h13) nc [86] (j13) 71 [85] (j12) 70 [84] (k13) 69 [83] (k12) 68 [82] (l13) 67 [81] (l12) 64 [80] (m13) nc [79] (m12) nc [78] (n13) 63 [77] (m11) 60 [76] (n12) 59 [75] (n11) 58 [74] (m10) 57 [73] (n10) 56 [58] (m4) nc [57] (n3) nc [56] (m3) 55 [55] (n2) 54 [54] (m2) 53 [53] (n1) 52 [52] (l2) 51 [51] (m1) 50 8 (b13) [1] 9 (c12) [2] 10 (a13) [3] 11 (b12) [4] 12 (a12) [5] 13 (11) [6] nc (a11) [7] nc (b10) [8] 14 (a4) [23] 15 (b4) [24] 16 (a3) [25] 17 (a2) [26] 18 (b3) [27] 21 (a1) [28] nc (b2) [29] nc (b1) [30] 22 (c2) [31] 25 (c1) [32] 26 (d2) [33] 27 (d1) [34] 28 (e2) [35] 29 (e1) [36] nc (f1) [39] nc (g2) [40] 30 (g3) [41] 31 (g1) [42] 32 (h3) [45] 33 (j1) [46] 34 (j2) [47] 35 (k1) [48] nc (k2) [49] nc (l1) [50] lab h lab g lab f lab e lab a lab b lab c lab d 3, 20, 37, 54 (a6,b6,f12,f13,h1,h2,m8,n8) [18, 19, 43, 44, 68, 69, 93, 94] 16, 33, 50, 67 (b8,c8,f2,f3,h11,h12,l6,m6) [12, 13, 37, 38, 62, 63, 87, 88] v cc gnd () ? pertain to 100-pin pga package 1 (c7) [16] input/clk . 78 (a10) [9] input . ..... 79 (b9) [10] input . ..... 80 (a9) [11] input ..... 83 (a8) [14] input . ..... 84 (b7) [15] input . ..... 2 (a7) [17] input . ..... 5 (c6) [20] input . ..... 6 (a5) [21] input . ..... 7 (b5) [22] input . ..... macrocell 73 ? 80 macrocell 72 macrocell 71 macrocell 70 macrocell 69 macrocell 68 macrocell 67 macrocell 66 macrocell 65 macrocell 57 ? 64 [] ? pertain to 100-pin pqfp package .
cy7c346b document #: 38-03037 rev. ** page 2 of 16 selection guide 7c346b-25 7c346b-35 maximum access time (ns) 25 35 pin configurations i/o top view plcc/clcc 7 64 53 11 12 10 98 43 42 44 45 46 21 22 24 23 25 13 14 41 40 21 26 27 18 19 17 16 15 20 28 29 31 30 32 33 36 35 37 38 39 34 52 51 49 50 48 47 c346b ? 2 53 54 55 60 58 59 57 56 66 65 63 64 62 67 61 input/clk i/o i/o i/o v cc inp /clk inp gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o v cc inp gnd inp i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o pga bottom view c346b ? 3 inp inp i/o i/o i/o i/o i/o i/o l k j h g f e d c b a 1 2 3 4 5 6 7 9 10 11 7c346b 7c346b i/o i/o i/o inp 8 i/o i/o i/o i/o i/o i/o i/o v cc 12 13 n m inp i/o inp inp inp i/o i/o gnd gnd v cc v cc i/o i/o i/o inp gnd i/o i/o v cc v cc gnd gnd i/o i/o i/o inp gnd inp i/o inp inp i/o inp v cc inp inp inp 74 73 72 71 70 69 68 84 83 82 81 80 79 78 77 76 75 input input v cc v cc input input input i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd gnd i/o i/o v cc v cc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o input input input gnd gnd input input input input v cc v cc input input input i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o v cc v cc i/o i/o gnd gnd i/o i/o i/o i/o i/o i/o i/o input gnd gnd input input input i/o i/o i/o
cy7c346b document #: 38-03037 rev. ** page 3 of 16 pin configurations (continued) top view pqfp 72 71 69 70 68 2 3 1 36 35 12 13 15 14 16 4 5 34 33 67 66 17 26 9 10 8 7 6 11 27 28 30 29 31 32 61 60 58 59 57 65 64 56 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o input i/o input v cc v cc input input input i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o input input input 62 63 i/o i/o i/o gnd i/o gnd gnd i/o i/o v input input i/o i/o gnd gnd input input input i/o i/o i/o i/o v cc v cc input input input i/o i/o i/o i/o i/o i/o 18 19 20 21 22 23 24 25 55 54 53 52 51 50 49 48 47 46 45 37 38 39 40 41 42 43 cc 44 80 79 77 78 76 75 74 73 95 96 97 98 100 99 81 82 83 84 85 86 94 93 92 91 90 89 88 87 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o input gnd gnd input input/clk input i/o gnd v cc c346b ? 4 i/o i/o i/o v cc i/o i/o i/o v cc 7c346b
cy7c346b document #: 38-03037 rev. ** page 4 of 16 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to+135 c ambient temperature with power applied............................................. ? 65 c to+135 c maximum junction temperature (under bias).................................................................. 150 c supply voltage to ground potential [1] ............. ? 2.0v to+7.0v dc output current per pin [1] .................... ? 25 ma to+25 ma dc input voltage [1] ........................................ ? 2.0v to + 7.0v operating range range ambient temperature v cc commercial 0 c to +70 c 5v 5% industrial ? 40 c to +85 c 5v 10% electrical characteristics over the operating range parameter description test conditions min. max. unit v cc supply voltage maximum v cc rise time is 10 ms 4.75(4.5) 5.25(5.5) v v oh output high voltage i oh = ? 4 ma dc [2] 2.4 v v ol output low voltage i ol = 8 ma dc [2] 0.45 v v ih input high voltage 2.0 v cc +0.3 v v il input low voltage ? 0.3 0.8 v i ix input current v i = v cc or ground ? 10 +10 a i oz output leakage current v o = v cc or ground ? 40 +40 a t r recommended input rise time 100 ns t f recommended input fall time 100 ns capacitance parameter description test conditions max. unit c in input capacitance v in = 0v, f = 1.0 mhz 10 pf c out output capacitance v out = 0v, f = 1.0 mhz 20 pf notes: 1. minimum dc input is ? 0.3v. during transactions, the inputs may undershoot to ? 2.0v or overshoot to 7.0v for input currents less then 100 ma and periods shorter than 20 ns. 2. the i oh parameter refers to high-level ttl output current; the i ol parameter refers to low-level ttl output current. ac test loads and waveforms 3.0v 5v output r1 464 ? r2 250 ? 50 pf including jig and scope gnd 90% 10% 90% 10% 6ns 6 ns 5v output r1 464 ? r2 250 ? 5pf including jig and scope (a) (b) output 1.75v equivalent to: th venin equivalent (commercial/military) all input pulses c346b ? 6 c346b ? 7 163 ?
cy7c346b document #: 38-03037 rev. ** page 5 of 16 logic array blocks there are 8 logic array blocks in the cy7c346b. each lab consists of a macrocell array containing 16 macrocells, an ex- pander product term array containing 32 expanders, and an i/o block. the lab is fed by the programmable interconnect array and the dedicated input bus. all macrocell feedbacks go to the macrocell array, the expander array, and the program- mable interconnect array. expanders feed themselves and the macrocell array. all i/o feedbacks go to the programmable in- terconnect array so that they may be accessed by macrocells in other labs as well as the macrocells in the lab in which they are situated. externally, the cy7c346b provides 20 dedicated inputs, one of which may be used as a system clock. there are 64 i/o pins that may be individually configured for input, output, or bidirec- tional data flow. programmable interconnect array the programmable interconnect array (pia) solves intercon- nect limitations by routing only the signals needed by each logic array block. the inputs to the pia are the outputs of every macrocell within the device and the i/o pin feedback of every pin on the device. figure 1. cy7c346b internal timing model logic array control delay t lac expander delay t exp clock delay t ic t rd t comb t latch input delay t in register output delay t od t xz t zx logic array delay t lad feedback delay t fd output input c346b ? 9 system clock delay t ics t rh t rsu t pre t clr pia delay t pia i/o delay t io
cy7c346b document #: 38-03037 rev. ** page 6 of 16 design recommendations operation of the devices described herein with conditions above those listed under ? maximum ratings ? may cause per- manent damage to the device. this is a stress rating only and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this data sheet is not implied. exposure to absolute maximum rat- ings conditions for extended periods of time may affect device reliability. the cy7c346b contains circuitry to protect device pins from high static voltages or electric fields, but normal pre- cautions should be taken to avoid application of any voltage higher than the maximum rated voltages. for proper operation, input and output pins must be con- strained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic level (ei- ther v cc or gnd). each set of v cc and gnd pins must be connected together directly at the device. power supply de- coupling capacitors of at least 0.2 f must be connected between v cc and gnd. for the most effective decoupling, each v cc pin should be separately decoupled to gnd direct- ly at the device. decoupling capacitors should have good frequency response, such as monolithic ceramic types have. design security the cy7c346b contains a programmable design security fea- ture that controls the access to the data programmed into the device. if this programmable feature is used, a proprietary de- sign implemented in the device cannot be copied or retrieved. this enables a high level of design control to be obtained since programmed data within eprom cells is invisible. the bit that controls this function, along with all other program data, may be reset simply by erasing the entire device. the cy7c346b is fully functionally tested and guaranteed through complete testing of each programmable eprom bit and all internal logic elements thus ensuring 100% program- ming yield. the erasable nature of these devices allows test programs to be used and erased during early stages of the production flow. the devices also contain on-board logic test circuitry to allow verification of function and ac specification once encapsulat- ed in non-windowed packages. typical i cc vs. f max output drive current 400 300 200 100 1 khz 10 khz 100 khz 1 mhz i cc maximum frequency 10 mhz 0 50 mhz 100 hz active (ma) typ. v cc = 5.0v room temp. c346b ? 10 01 2 3 4 i output current (ma) typical v o output voltage (v) 250 200 150 100 50 5 o i oh i ol v cc = 5.0v room temp. c346b ? 11
cy7c346b document #: 38-03037 rev. ** page 7 of 16 timing considerations unless otherwise stated, propagation delays do not include expanders. when using expanders, add the maximum ex- pander delay t exp to the overall delay. similarly, there is an additional t pia delay for an input from an i/o pin when com- pared to a signal from straight input pin. when calculating synchronous frequencies, use t su if all in- puts are on dedicated input pins. when expander logic is used in the data path, add the appropriate maximum expander delay, t exp to t su . determine which of 1/(t wh + t wl ), 1/t co1 , or 1/(t exp + t su ) is the lowest frequency. the lowest of these frequencies is the maximum data path frequency for the syn- chronous configuration. when calculating external asynchronous frequencies, use t as1 if all inputs are on the dedicated input pins. when expander logic is used in the data path, add the appro- priate maximum expander delay, t exp to t as1 . determine which of 1/(t awh + t awl ), 1/t aco1 , or 1/(t exp + t as1 ) is the lowest frequency. the lowest of these frequencies is the maximum data path frequency for the asynchronous config- uration. the parameter t oh indicates the system compatibility of this device when driving other synchronous logic with positive input hold times, which is controlled by the same synchro- nous clock. if t oh is greater than the minimum required input hold time of the subsequent synchronous logic, then the de- vices are guaranteed to function properly with a common synchronous clock under worst-case environmental and supply voltage conditions. commercial and industrial external synchronous switching characteristics over operating range 7c346b-25 7c346b-35 parameter description min. max. min. max. unit t pd1 dedicated input to combinatorial output delay [3] 25 35 ns t pd2 i/o input to combinatorial output delay [3] 40 55 ns t su global clock set-up time 15 25 ns t co1 synchronous clock input to output delay [3] 14 20 ns t h input hold time from synchronous clock input 0 0 ns t wh synchronous clock input high time 8 12.5 ns t wl synchronous clock input low time 8 12.5 ns f max maximum register toggle frequency [4] 62.5 40 mhz t cnt minimum global clock period 20 30 ns t odh output data hold time after clock 2 2 ns f cnt maximum internal global clock frequency [5] 50 33.3 mhz commercial and industrial external asynchronous switching characteristics over operating range 7c346b ? 25 7c346b ? 35 parameter description min. max. min. max. unit t aco1 asynchronous clock input to output delay [3] 25 35 ns t as1 dedicated input or feedback set-up time to asynchronous clock input 5 10 ns t ah input hold time from asynchronous clock input 6 10 ns t awh asynchronous clock input high time [6] 11 16 ns t awl asynchronous clock input low time [6] 9 14 ns t acnt minimum internal array clock frequency 20 30 ns f acnt maximum internal array clock frequency [5] 50 33.3 mhz notes: 3. c1 = 35 pf. 4. the f max values represent the highest frequency for pipeline data. 5. this parameter is measured with a 16-bit counter programmed into each lab. 6. this parameter is measured with a positive-edge-triggered clock at the register. for negative-edge clocking, the t ach and t acl parameter must be swapped.
cy7c346b document #: 38-03037 rev. ** page 8 of 16 commercial and industrial internal switching characteristics over operating range 7c346b-25 7c346b-35 parameter description min. max. min. max. unit t in dedicated input pad and buffer delay 5 11 ns t io i/o input pad and buffer delay 6 11 ns t exp expander array delay 12 20 ns t lad logic array data delay 12 14 ns t lac logic array control delay 10 13 ns t od output buffer and pad delay [3] 5 6 ns t zx output buffer enable delay [3] 10 13 ns t xz output buffer disable delay [7] 10 13 ns t rsu register set-up time relative to clock signal at register 6 12 ns t rh register hold time relative to clock signal at register 4 8 ns t latch flow through latch delay 3 4 ns t rd register delay 1 2 ns t comb transparent mode delay 3 4 ns t ic asynchronous clock logic delay 14 16 ns t ics synchronous clock delay 3 1 ns t fd feedback delay 1 2 ns t pre asynchronous register preset time 5 7 ns t clr asynchronous register clear time 5 7 ns t pia programmable interconnect array delay time 14 20 ns note: 7. c1 = 5 pf.
cy7c346b document #: 38-03037 rev. ** page 9 of 16 switching waveforms external combinatorial dedicated input/ i/o input combinatorial output c346b-12 t pd1 /t pd2 c346b-13 t wl t su t h logic array t wh external synchronous clock at register synchronous synchronous logic array data from registered clock pin outputs t co1 external asynchronous t ah t as1 t awh t awl dedicated inputs or registered feedback asynchronous clock input c346b-14 internal combinatorial t in io t exp t lac ,t lad c346b-15 t comb t od input pin i/o pin logic array logic array output input array delay expander output pin t
cy7c346b document #: 38-03037 rev. ** page 10 of 16 switching waveforms (continued) internal asynchronous t io t awh t awl t f t in t ic t rsu t rh t rd ,t latch t fd t clr ,t pre t fd clock pin logic array logic array clock from data from clock into logic array register output to another lab t pia to local lab register output logic array c346b-16 t r t in t ics t rsu t rh c346b-17 system cl ock pin system clock at register data from logic array internal synchronous c346b-18 t xz t zx t od high impedance state clock from logic array logic array data from output pin t rd internal synchronous
cy7c346b document #: 38-03037 rev. ** page 11 of 16 max is a registered trademark of altera corporation. ordering information speed (ns) ordering code package name package type operating range 25 cy7c346b-25hc/hi h84 84-pin windowed leaded chip carrier commercial/industrial cy7c346b-25jc/ji j83 84-lead plastic leaded chip carrier cy7c346b-25nc/ni n100 100-lead plastic quad flatpack cy7c346b-25rc/ri r100 100-pin windowed ceramic pin grid array 35 cy7c346b-35hc/hi h84 84-pin windowed leaded chip carrier commercial/industrial cy7c346b-35jc/ji j83 84-lead plastic leaded chip carrier CY7C346B-35NC/ni n100 100-lead plastic quad flatpack cy7c346b-35rc/ri r100 100-pin windowed ceramic pin grid array
cy7c346b document #: 38-03037 rev. ** page 12 of 16 package diagrams 84-leaded windowed leaded chip carrier h84 51-80081
cy7c346b document #: 38-03037 rev. ** page 13 of 16 package diagrams (continued) 84-lead plastic leaded chip carrier j83 51-85006-a
cy7c346b document #: 38-03037 rev. ** page 14 of 16 package diagrams (continued) 100-lead plastic quad flatpack n100 51-85052-a
cy7c346b document #: 38-03037 rev. ** page 15 of 16 ? cypress semiconductor corporation, 1997. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagrams (continued) 100-pin windowed ceramic pin grid array r100 51-80010-b
cy7c346b document #: 38-03037 rev. ** page 16 of 16 document title: cy7c346b 128-macrocell max ? epld document number: 38-03037 rev. ecn no. issue date orig. of change description of change ** 106460 07/11/01 szv change from spec number: 38-00861 to 38-03037

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